This invention relates to a novel domino-logic decoder. More specifically, this invention relates to a modified domino decoder which includes circuitry which may be utilized in other types of electrical applications, and which does not suffer from body effect.
Domino logic is a type of sequential logic circuitry oftentimes utilized in decoders. Decoders are often used to select the appropriate portion of a computer memory depending upon the particular address input to the decoder. Domino logic usually refers to a cascaded set of dynamic logic blocks in which each stage evaluates and causes the next stage to evaluate, in the same manner that a stack of dominos fall. Any number of logic stages may be cascaded, but it must be possible to evaluate the sequence within a certain clock phase. A single clock can be used to precharge and evaluate all logic gates within a block.
One type of prior art domino decoder includes a plurality of input lines which are each input to a transistor. The transistors are coupled together in series and connected to a ground potential at one end. The decoder includes two phases of operation: a pre-charge phase, and a strobing phase. When the decoder is enabled, the transistors begin charging to the values which are input by the input lines. A discharge transistor is coupled between the input transistors and ground to prevent the transistors from discharging to ground during the pre-charge phase. A node adjacent to the top transistor charges up with time since there is no path to ground. During the strobing phase, a strobe signal disables the discharge transistor. The node adjacent to the top transistor is discharged across each of the input transistors sequentially to produce the output signal, which indicates that that particular portion of the decoder has been selected. Since the node must discharge across each of the transistors in the stack, the total discharge time increases with the number of transistors. The speed of this type of domino logic is thus limited by the number of input lines, which corresponds to the number of transistors across which a node must discharge. The decoding time affects how quickly a memory address may be accessed. Thus, it is important that the decoding time be minimized in order to increase a computer's overall processing speed.
Another problem with this type of domino-logic decoder is that it suffers from body effect. Body effect refers to the modification of a transistor's threshold voltage with a voltage difference between the source and the substrate. For instance, if a number of transistors are coupled in series, the transistor at the output will switch slower than the other transistors if the source potential of this transistor is not the same as the substrate. The switching time of the series is reduced because the transistor at the output takes longer to discharge.
The difficulties in the preceding are not intended to be exhaustive but rather are among many which may tend to reduce the usefulness of prior art domino-logic decoders. Other noteworthy problems may also exist; however, those presented above should be sufficient to demonstrate that domino decoders appearing in the past will admit to worthwhile improvement.
It is therefore a general object of the invention to provide a novel domino-logic decoder which will obviate or minimize difficulties of the type previously described.
It is a specific object of the invention to provide a domino-logic decoder which can decode an input in an amount of time which is substantially independent of the number of the inputs.
It is another object of the invention to provide a domino-logic decoder which reliably decodes an input in a shorter amount of time than domino decoders of the prior art.
It is still another object of the invention to provide a domino-logic decoder which does not suffer from body effect.